FIG. 1 shows a first example of a voltage step-up device used in integrated circuits, for example, to convert digital signals originating from digital blocks processing data under a relatively low voltage Vdd, sent to so-called analog blocks processing the data under a voltage Vcc with an amplitude relatively higher than voltage Vdd.
In the following description, and unless otherwise mentioned, on-state voltage drops in switches will be neglected, knowing that levels Vcc, Vdd and the ground are in practice only reached to within the voltage drops in the series resistors of the on-state switches.
The device of FIG. 1 comprises two parallel branches between two terminals 1 and 2 of application of a relatively high power supply voltage Vcc corresponding to the states desired for an output signal Vout. Each branch comprises three transistors in series, respectively, a P-channel transistor P1 or P2, and two N-channel transistors N1, N3 or N2, N4. The sources of transistors P1 and P2 are connected to terminal 1 while their respective drains are connected to the respective drains of transistors N3 and N4 as well as to the gate of the transistor P1 or P2 of the other branch. The sources of transistors N3 and N4 are connected to the respective drains of transistors N1 and N2 having their sources connected to ground 2. A digital input signal Vin switching between two states 0 and 1 (state 1 being shown by voltage Vdd lower than said voltage Vcc) is applied on a terminal IN connected to the respective gates of transistors N1 and N2 by being inverted (inverter 5) for one of the two branches (for example, for the connection to transistor N2). The drain of transistor P2 defines an output terminal 4 providing signal Vout. Inverter 5 is an inverter supplied with voltage Vdd. A reference voltage provided by a bias source 6 (REF) is applied to the common gates of transistors N3 and N4 so that they are respectively turned on or turned off according to the conduction or to the blocking of the transistor N1 or N2 with which they are associated.
The structure of FIG. 1 corresponds to a cell of locking, by transistors P1 and P2, of the level present at input IN on output terminal 4. An inverse output can be taken on drain 7 of transistor P1.
When a signal at state 0 (ground) is present at input IN of the device, transistor N1 is off while transistor N2 is on due to the inversion performed by inverter 5. The on state of transistor N2 is transferred to transistor N4, which has its gate biased to a voltage selected to be greater than the threshold voltage of transistor N4 plus the voltage drop in transistor N2 in the on state, while transistor N3 remains off. The voltage of terminal 4 is drawn to ground by on transistors N4 and N2. This low voltage being transferred onto the gate of transistor P1, said transistor is turned on, which locks the off state of transistor P2 by bringing its gate to a level close to voltage Vcc. The voltage obtained at output 4 thus is a low state 0 (close to ground) and output 7 is at a high level close to level Vcc.
In the presence of a high state on input IN, transistors N1 and N3 are on while transistors N2 and N4 are off. The conduction of transistors N3 and N1 causes that of transistor P2 by drawing its gate towards ground, which raises the level of output terminal 4 to a voltage close to level Vcc. Transistor P1 is locked in an off state by this level close to the level Vcc applied on its gate. A high state is thus effectively obtained at output 4 and a low state is obtained at output 7.
In certain applications, the used MOS transistors are distinguished according to their respective breakdown voltage which depends, in practice, on their oxide thickness. The breakdown voltage of the transistors varies in the same direction as the oxide thickness. The transistor switching speed however varies inversely to this oxide thickness. A way to compensate for this thickness is to increase the transistor size (gate width to length ratio—W/L).
Reference will be made hereafter to digital transistors to designate transistors supporting a relatively low voltage Vdd (relatively thin gate oxide—simple oxide) and to analog transistors to designate transistors supporting voltage Vcc (relatively thick gate oxide—double oxide).
In the example of FIG. 1, transistors N1 and N2 may be digital transistors since the voltage drop introduced by transistors N3 and N4 is sufficient to limit the voltage across transistors N1 and N2. Transistors P1, P2, N3, and N4 however are analog transistors to stand voltage Vcc at their respective terminals.
FIG. 2 is a schematic block diagram of an example of application to an interface 12 intended for a level conversion between a core 10 of an integrated circuit and a memory 20 of another integrated circuit. In such an application, the states of data signals DATA1 to DATAn between levels 0 and Vdd is to be adapted to the voltage levels used by memory 20 between 0 and Vcc. A differential clock signal CLK provided by core 10 is to also be transmitted to memory 20. In the case of a DDR-type memory, the two edges (rising and falling) of the clock signal are exploited by memory 20, which uses processing signal CLK and its inverse (inverter 15).
Input/output circuit 12 shown in FIG. 2 comprises as many level shifters 30 (LS) as there are signals to be converted. Further, in the application to memories, the respective outputs OUT of level shifters 30 cross pre-amplification circuits 31 (PREDRIVER), then buffer amplifiers 32 (BUFF) before provision of the signals on output terminal 14 of circuit 12. Each terminal 14 is connected by a conductor 17 of a printed circuit board to an input terminal 28 of memory 20. As for converted clock signal HCLK, it is restored by means of a comparator 24 (COMP) shaping the signals provided on the two terminals 28 corresponding to the two processing lines of signals CLK and of its inverse.
Input signals CLK, DATA1, and DATAn are provided by circuits supplied by voltage Vdd, which thus corresponds to the voltage of input stages 35 of level shifters 30. All the circuits downstream of level shifters 30, as well as output stages 36 of these circuits, are powered by relatively high voltage Vcc. For example, voltage Vdd is on the order of one volt while voltage Vcc is 2.5 volts, or even 1.8 volts.
What has been discussed in relation with a digital block 10 and a so-called analog block 20 of two distinct electronic circuits connected to each other by conductors 17 of a printed circuit board also applies to two blocks of a same integrated circuit connected by conductive tracks.
In interfaces intended for memories, the conventional level shifters 30 are of the type of those illustrated in FIG. 1. Such circuits enable operation at frequencies up to a few hundreds of megahertz.
A disadvantage of the level shifter of FIG. 1 is that to operate at frequencies of several hundreds of megahertz, analog transistors must be of relatively large size. This increases the dynamic power consumption, generates significant current surges and bounces on the power supplies. This thus disturbs the signal.
Another disadvantage of the circuit of FIG. 1 is that the duty cycle of the output signal is dependent on temperature, on voltages Vcc and Vdd, on the manufacturing conditions and on the differences between the N-channel and P-channel MOS transistors, as well as between transistors N1 and N2.
Another disadvantage of the circuit of FIG. 1 is that a possible supply noise on the digital signal may generate an output phase shift. In other words, a variation of the propagation time between terminals IN and OUT translates as a phase noise on the signal.
Such constraints results in that, in practice, a level shifter such as illustrated in FIG. 1 is limited to a frequency from 3 to 400 megahertz.
One of the constraints of the application to a memory such as illustrated in FIG. 2 is that data signals (non-periodic) are to be provided to the memory synchronously with the clock signal. Accordingly, the propagation time in the input/output circuits of the differential clock obtained from signal CLK are to be the same as in the input/output circuits processing data. This results in a practical obligation to have identical level shifters both for the data and for the clock signal, and thus two level shifters for the clock signal.
FIG. 3 shows a second example of level shifter, described in US patent application publication no. 2004/263220.
The circuit of FIG. 3 comprises two inverters 41 and 42 formed of digital transistors (supplied by voltage Vdd) and respectively receiving signal IN to be reproduced on an output terminal OUT and inverse NIN of this signal. Signals IN and NIN may originate from flip-flops of the digital circuit if the application requires a perfect synchronization between these signals. The respective output terminals 43 and 44 of the inverters are each connected to a (positive) terminal 1 of application of voltage Vcc by two transistors in series, respectively N-channel transistors N3 or N4, and P-channel transistors P1 or P2, the P-channel transistors being on the side of terminal 1. Each output 43 or 44 is further connected to a first electrode of a capacitive element C3 or C4 having its second electrode connected to the gate of transistor N4 or N3 of the other branch. The respective gates of transistors N3 and N4 are further connected, by resistive elements R3 and R4, to a terminal 45 of application of a bias voltage (positive in this example) Vbias. Transistor P2 has its gate connected to the drain of transistor P1 while its own drain forms output terminal OUT. The gate of transistor P1 is connected by a resistor R1 to the gate of transistor P2 and by a capacitor C1 to terminal 1.
The function of capacitive elements C3 and C4 is to directly transmit onto the gates of transistors N3 and N4 the edges provided by inverters 41 and 42, which enables accelerating the level shifter speed. Resistors R3 and R4 take part in the creation of resistive and capacitive cells with elements C3 and C4, introducing a time constant in the discharge of the gate of transistor N3 or N4 which has been brought to the high state.
Resistor R1 and capacitor C1 introduce a delay in the switching of transistor P1 with respect to that of transistor P2, which increases the switching speed of transistor P2.
Bias voltage Vbias, selected to be greater than the threshold voltage of transistor N4, is lower than the sum of this threshold voltage and of supply voltage Vdd on the digital side.
In the circuit of FIG. 3, transistors P1, P2, N3, and N4 all are analog transistors but are made fast due to a capacitive control. Further, they are of smaller size, generate less power consumption, less current surge, and thus less noise on the power supplies. Further, the propagation time of the rising and falling edges (and thus the duty cycle) becomes independent from voltage Vdd, from temperature, and from the manufacturing conditions.
FIG. 4 schematically shows an example of the forming of a voltage source providing bias voltage Vbias on node 45 of the circuit of FIG. 3. This voltage source is formed of a series association of a P-channel MOS transistor P5, of a resistor R5, and of an N-channel MOS transistor N6 between terminals 1 and 2 of application of voltage Vcc. Transistor P5 is diode-assembled, its gate being connected to its drain, itself connected to a first terminal of resistor R5. Transistor N6 is also diode-assembled, its gate being connected to its drain, itself connected to the other end of resistor R5 and defining terminal 45 of provision of voltage Vbias. Transistors P5 and N6 are analog transistors.
A disadvantage of the level shifter of FIG. 3 is that a phase jitter appears in case of a non-periodic input signal IN.
This phase jitter in particular originates from the diode (even delayed) formed by transistor P1, which results in that the gate level of transistor P2 keeps in memory (builds up the history) of past switchings. As a result, the longer the input signal remains in a steady state, the more the level of this gate increases to tend towards level Vcc decreased by the threshold voltage of transistor P2 (typically on the order of 0.2 V). Accordingly, if the input signal does not switch periodically, the propagation time in the level shifter depends on the input signal. Such a phenomenon does not occur for a periodic clock signal (the gate of transistor P2 discharges with the same periodicity as it charges), but causes a phase jitter in the case of a non-periodic signal (typically, a data signal). This reduces the acquisition window (time for which it is certain to have the data at state 1 or 0) due to an increase in uncertainties about the state of the datum.
In other words, such a level shifter has, over that of FIG. 1, the advantage of being fast for the processing of a clock signal, but is not appropriate for a pseudo-random input signal, even if the edges of this input signal are synchronous with a clock signal. Now, this is especially the case in the application of data to be converted by means of an input/output circuit of the type illustrated in FIG. 2 and more generally as soon as the signal to be converted is not a clock signal.